In this tutorial, we will be exploring the IC Validator PERC VUE Demo Part 6, which is a powerful tool provided by Synopsys for physical verification and signoff of integrated circuits. This tool is specifically designed to help IC designers ensure the reliability and manufacturability of their designs before tape-out.
Part 6 of the IC Validator PERC VUE Demo focuses on the visualization of design rule violations and potential manufacturing issues using the PERC VUE interface. By using this interface, designers can quickly identify and fix any violations or potential issues, ensuring that their designs meet all necessary design rules and manufacturing constraints.
To begin, open the IC Validator PERC VUE Demo and load your design layout. Once the layout is loaded, navigate to the PERC VUE interface by selecting the “PERC VUE” option from the toolbar. This will launch the PERC VUE interface, where you can view and analyze design rule violations and potential manufacturing issues.
In the PERC VUE interface, you will see a detailed view of your design layout, with highlighted design rule violations and potential issues marked in red. These violations can include spacing violations, metal density violations, via enclosure violations, and many more. By clicking on these violations, you can view more detailed information about each violation, including its location, severity, and recommended fix.
In addition to design rule violations, the PERC VUE interface also provides visualization of manufacturing issues, such as lithography hotspots, etch hotspots, and CMP hotspots. These issues can have a significant impact on the manufacturability of your design and may need to be addressed before tape-out. By identifying and fixing these issues early in the design process, you can avoid costly re-spins and delays in the manufacturing process.
To fix design rule violations and potential manufacturing issues in the PERC VUE interface, you can use a variety of editing tools, such as the “Ruler” tool, the “Edit” tool, and the “Delete” tool. These tools allow you to make precise modifications to your design layout, ensuring that all violations are corrected and all potential issues are resolved.
Once you have fixed all design rule violations and potential manufacturing issues in the PERC VUE interface, you can generate a detailed design rule check (DRC) report to verify that your design now meets all necessary design rules and manufacturing constraints. This report can be shared with other team members or stakeholders to ensure that everyone is on the same page before tape-out.
In conclusion, the IC Validator PERC VUE Demo Part 6 is a valuable tool for IC designers looking to ensure the reliability and manufacturability of their designs. By using the PERC VUE interface to visualize and analyze design rule violations and potential manufacturing issues, designers can quickly identify and fix any issues before tape-out, saving time and reducing the risk of costly re-spins.
